It is established that multilayered printed circuit boards (PCBs), laminate chip carriers, and the like organic products permit formation of multiple circuits in a minimum volume or space. These structures are known to comprise a stack of electrically conductive layers of signal, ground and/or power planes (lines) separated from each other by a layer of organic dielectric material. The lines are often in electrical contact with each other by plated holes passing through the dielectric layers. The plated holes are often referred to as “vias” if internally located, “blind vias” if extending a predetermined depth within the board from an external surface, or “plated-thru-holes” (PTHs) if extending substantially through the board's full thickness. By the term “thru-hole” as used herein is thus meant to include all three types of such board openings.
Methods for making such PCBs, chip carriers and the like typically comprise fabrication of separate inner-layer circuits (circuitized layers), which are formed by coating a photosensitive layer or film over a copper layer of a copper clad inner-layer base material. The organic photosensitive coating is imaged, developed and the exposed copper is etched to form conductor lines. After etching, the photosensitive film is stripped from the copper leaving the circuit pattern on the surface of the inner-layer base material. This processing is also referred to as photolithographic processing in the PCB art and further description is not deemed necessary. Following the formation of individual inner-layer circuits, a multilayer stack is formed by preparing a lay-up of inner-layers, ground planes, power planes, etc., typically separated from each other by a dielectric, organic pre-preg typically comprising a layer of glass (typically fiberglass) cloth impregnated with a partially cured material, typically a B-stage epoxy resin. Such an organic material is also referred to in the industry as “FR-4” dielectric material. The top and bottom outer layers of the stack usually comprise copper clad, glass-filled, epoxy planar substrates with the copper cladding comprising exterior surfaces of the stack. The stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin. The stack so formed typically has metal (usually copper) cladding on both of its exterior surfaces. Exterior circuit layers are formed in the copper cladding using procedures similar to the procedures used to form the inner-layer circuits. A photosensitive film is applied to the copper cladding. The coating is exposed to patterned activating radiation and developed. An etching solution such as cupric chloride is then used to remove copper bared by the development of the photosensitive film. Finally, the remaining photosensitive film is removed to provide the exterior circuit layers. Elements of such layers, e.g., conductive pads, may be used then to have electrical components mounted thereon. One such example of an electrical component is a chip carrier, or a even a single semiconductor chip, both of which may be mounted on the external pads using solder balls or some other known process, e.g., wire-bonding.
Thru-holes (or interconnects) of the above type are used to electrically connect individual circuit layers within the structure to each other and to the outer surfaces and typically pass through all or a portion of the stack. Thru-holes may be formed prior to the formation of circuits on the exterior surfaces by drilling holes through the stack at appropriate locations. Alternatively, such holes may be formed within the individual circuitized layers prior to incorporation within the multi-layered structure and final lamination thereof. In both methods, the bare hole walls are usually subjected to at least one pre-treatment step after which the walls are catalyzed by contact with a plating catalyst and metallized; typically by contact with an electro-less or electrolytic copper plating solution. If the thru-holes are PTHs, interconnections are thus formed between selected ones of the circuitized layers of the multilayered final product which have one or more conductive lines or elements in contact with the inner conductive layer of the PTHs. If the thru-holes are individually formed within selected layers and then coupled to one another during product stacking, connectivity is accomplished preferably using a conductive paste or the like. Such pastes are known to include a highly conductive metal such as silver in the form of flakes. Following formation of the conductive thru-holes in multilayered structures such as PCBs in which the thru-holes are provided as PTHs, exterior circuits (outer-layers) are formed using the procedure described above. Such external formation may also occur when stacking layers already having thru-holes formed therein, albeit it is possible to form the two outer conductive layers prior to stacking and lamination. When external components are mounted on the substrate and coupled to the external conductors, e.g., pads, thereon, it is thus seen that said components are then capable of being electrically coupled to other such components through the substrate's internal circuitry.
As stated, semiconductor chips and/or other electrical components are mounted at appropriate locations on the exterior circuit layers of the multilayered stack. In some examples, such components are mounted and electrically coupled using the above mentioned solder balls, one form of which is referred to in the industry as ball grid array (BGA) technology. For PCBs, these components may include capacitors, resistors, and even chip carriers. For chip carriers having multilayered substrates, a chip is often solder bonded to the carrier laminate substrate's upper surface and the carrier is in turn solder bonded to an underlying substrate, typically a PCB. In either form (PCB or chip carrier), the components are in electrical contact with the circuits within the structure through the conductive thru-holes, as desired. The solder pads are typically formed by coating an organic solder mask coating over the exterior circuit layers. The solder mask may be applied by screen coating a liquid solder mask coating material over the surface of the exterior circuit layers using a screen having openings defining areas where solder mount pads are to be formed. Alternatively, a photoimageable solder mask may be coated onto the exterior surfaces and exposed and developed to yield an array of openings defining the pads. The openings are then coated with solder using processes known to the art such as wave soldering. Examples of organic products such as defined above are shown in the patents listed below, as are substrates of the non-organic (ceramic) type.
In U.S. Pat. No. 6,828,514, issued Dec. 07, 2004, there is defined a multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections there-between. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. This patent is assigned to the same Assignee as the instant invention.
In U.S. Pat. No. 6,815,837, issued Nov. 09, 2004, there is defined an electronic package (e.g., a chip carrier) and information handling system utilizing same wherein the package substrate includes an internally conductive layer coupled to an external pad and of a size sufficiently large enough to substantially prevent cracking, separation, etc. of the pad when the pad is subjected to a predetermined tensile pressure. This patent is also assigned to the same Assignee as the instant invention.
In U.S. Pat. No. 6,809,269, issued Oct. 26, 2004, there is defined a circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith. One example of a product using this technology is a chip carrier. This patent is also assigned to the same Assignee as the instant invention.
In U.S. Pat. No. 6,762,496, issued Jul. 13, 2004, there is described a sintered aluminum nitride substrate which has a via hole and an internal electrically conductive layer with, allegedly, high thermal conductivity and high adhesion strength between the sintered aluminum nitride substrate and the internal electrically conductive layer or the via hole. The substrate consists of an internal electrically conductive layer, at least one electrically conductive via hole formed between the internal electrically conductive layer and at least one surface of the substrate, wherein the thermal conductivity of the aluminum nitride sintering product at 25 degrees Celsius (C.) is described as being 190 W/mK or more, with a corresponding adhesion strength between the aluminum nitride sintering product and the internal electrically conductive layer also mentioned.
In U.S. Pat. No. 6,641,898, issued Nov. 4, 2003, there is described a heated and pressed printed wiring board which is made by filling “via” holes formed in layers of insulating film of the wiring board with an interlayer conducting material. The insulating film is stacked with conductor patterns, and each conductor pattern closes a hole. The interlayer conducting material forms a solid conducting material in the holes after a heating a pressing procedure. The solid conducting material includes two types of conducting materials. The first type of conducting material includes a metal, and the second type of conductive material includes an alloy formed by the metal and conductor metal of the conductor patterns. The first type of conducting material includes indium particles, tin and silver wherein tin accounts for approximately 20-80 weight percentage of the solid conductive material, and the second type of conducting material includes an alloy comprised of the solid conductive material and the conductor metal. The conductor patterns are electrically connected reliably without relying on mere mechanical contact.
In Published Patent Application 2002/0050586, issued May 2, 2002, there is described an electro-conductive paste for use in making ceramic substrates containing from about 5 to 18 percent by weight of an organic vehicle consisting of a solvent and a binder, from about 80 to 93 percent by weight of an electro-conductive metal powder in a spherical or granular shape and with a particle diameter in the range of about 0.1 to 50 microns, and from about 2 to 10 percent by weight of a resin powder with a particle diameter in the range of about 0.1 to 50 microns which is insoluble in the solvent and has a low level of water absorption. This paste may be used for forming via hole conductors to be converted to external electrode terminals for the resulting ceramic products.
In U.S. Pat. No. 6,120,708, issued Sep. 19, 2000, there is described a conductive paste for forming via-holes in a ceramic substrate, which paste contains about 80-94 weight percentage spherical or granular conductive metal powder having a particle size of about 0.1-50 microns, 1-10 weight percentage resin powder which swells in a solvent contained in the conductive paste and has a particle size of about 0.1-40 microns, and about 5-19 weight percentage of an organic vehicle. The paste allegedly hardly generates cracks during firing to thereby attain excellent reliability in electric conduction and which can provide a via-hole or through hole having excellent solderability and platability in a ceramic substrate structure.
In U.S. Pat. No. 5,891,283, issued Apr. 6, 1999, there is described a conductive paste for use in forming ceramic substrates in which the composition consists of an organic vehicle, copper powder and an organo-metallic resinate which includes, as the metal, at least one metal selected from the group consisting of Pt, Ni and Bi. The amount of the metal component in the organo-metallic resinate is in the range of about 0.1 to 5 weight percentage with respect to the total amount of the copper power and the metal component. The copper powder has preferably an average diameter in the range of about 2 to 30 microns.
The relative complexity of the above organic products (those including organic dielectric layers, including the aforementioned PCBs and laminate chip carriers) has increased significantly over the past few years, especially as such products increase in demand over those of the ceramic variety. For example, PCBs for mainframe computers may have as many as thirty-six layers of circuitry or more, with the complete stack having a thickness of as much as about 0.250 inch (250 mils). Laminate chip carriers, in turn, may have as many as fifteen circuit layers as part thereof. Such organic products are known with three or five mil (a mil being one thousandth of an inch) wide signal lines and twelve mil diameter thru-holes, but for increased circuit densification in many of today's products, the industry is attempting to reduce signal lines to a width of two mils or less and thru-hole diameters to two mils or less. Such high densification understandably mandates the most efficient means of interconnecting the respective layers in the smallest space available and using the best materials possible. As defined herein, the present invention is able to accomplish this.
It is believed that a method of making a circuitized substrate having organic dielectric material as part thereof which is able to provide enhanced interconnection between various conductive portions (e.g., layers) thereof would constitute a significant advancement in the art.